Method for fabricating semiconductor device

ABSTRACT

A method for fabricating a semiconductor device, comprising the steps of: forming an element on a silicon substrate; packaging the element; and annealing the packaged element before its transportation or long-term storage.

This application is the US national phase of international applicationPCT/JP02/12938 filed 10 Dec. 2002, which designated the US.PCT/JP02/12938 claims priority to JP Application No. 2001-376014 filed12 Dec. 2001. The entire contents of these applications are incorporatedherein by reference.

TECHNICAL FIELD

The present invention relates to a method for fabricating asemiconductor device. More particularly, it relates to a method forfabricating a semiconductor device capable of preventing defects in anelement of the semiconductor device while the semiconductor device isbeing packaged or exposed to an energy beam such as a cosmic ray duringtransportation or long-term storage.

RELATED ART AND OTHER CONSIDERATIONS

Solid-state image pickup devices as a type of semiconductor device havemade striking developments in function and performance such as increasein pixel number. FIG. 1 is a schematic cross section of a pixel of a CCD(charge-coupled device) of a type of solid-state image pickup device tobe mounted in a video camera or the like.

As shown in FIG. 1, the CCD is constructed such that pixels eachincluding a pair of a microlense 106 and a photodiode 102 are arrangedtwo-dimensionally on a silicon substrate. In FIG. 1, reference numeral101 denotes the silicon substrate, 102 a photodiode, 103 a CCD channel,104 a transfer electrode, 105 a planarization film, and 106 a microlens.Components other than the above shown in FIG. 1 e.g. a light-shieldingfilm and the like are not numbered for the sake of brevity.

An operation principle of the above CCD will now be explained briefly.As a light ray condensed by the microlens 106 enters the photodiode 102,electrons are generated through photoelectric conversion. The generatedelectrons are accumulated in the photodiode 102. Upon application of apredetermined voltage to the transfer electrode 104 after the lapse of apredetermined accumulation period, the accumulated electrons (charges)are read out into the CCD channel 103. Then, by applying a predeterminedpulse voltage to a group of transfer electrodes (not illustrated)arranged perpendicularly to a direction of the paper surface, theelectrons are transferred to the group of transfer electrodes. Thetransferred electrons are converted into a voltage signal by means ofanother element in a video camera so as to be taken out as an image.

In a process of fabricating a solid-state image pickup device such as aCCD, a trace quantity of impurity such as heavy metal impurity maypossibly be mingled in a silicon substrate. The mingled impurity locallyforms a defective level in the silicon substrate to increase a darkcurrent which appears itself as a white defect on a display screen. Thedefective level in the silicon substrate that arises from thefabricating process can be coped with by improving the fabricatingprocess, a treatment condition or the like.

Meanwhile, it is known that, when a CCD is airfreighted particularly viaa polar region, typically via the Arctic Circle, the number of whitedefectes increases by the influence of particles with great energiessuch as a cosmic ray, an x-ray, a radial ray or the like.

A cause for a white defect is considered to be an increase in interfacestate at the interface between a silicon substrate and a silicon oxidefilm. More specifically, electron-hole pairs are generated in a siliconsubstrate and in a silicon oxide film due to incidence of particles withgreat energies thereto. Electrons and holes generated in the siliconsubstrate diffuse in silicon and are recombined and eliminated, thuscausing no particular problem. Some of the electron-hole pairs generatedin the silicon oxide film, on the other hand, are immediately recombinedand eliminated. However, holes with less mobility among the otherelectron-hole pairs are trapped at a trapping center in the siliconoxide film or move in the film to reach the interface between thesilicon substrate and the silicon oxide film, creating a dangling bondin the silicon and thereby increasing interface state. The increase ininterface state also is considered to be responsible for the increase indark current.

For example, in the case where a CCD is incorporated into an apparatussuch as a video camera or the like in Japan and thereafter airfreightedto Europe or the like, a defect in the CCD is linked to a defect in aproduct as a whole in which the CCD is incorporated. Further, eventhough a white-defect correction-circuit is added to the apparatus tocorrect the CCD for the defect at the time of incorporation, a new whitedefect is generated by a cosmic ray when the product is airfreighted toEurope or the like after the CCD is corrected to cause a defect in thewhole product in which the CCD is incorporated. Also, in the case wherethe incorporation of the CCD into the apparatus is made in Europe, evenin a CCD shipped as a good one, a defect developed during airfreightcauses a defect in the whole product in which the CCD is incorporated.

Japanese Unexamined Patent Publication No. Hei 8(1996)-18025 discloses atechnique for rapidly eliminating electron-hole pairs generated in asilicon oxide film to prevent the increase in interface state. FIG. 2 isa schematic cross section of a pixel in a CCD disclosed in thepublication.

The CCD of FIG. 2 is different in structure from the typical CCD of FIG.1 in that a BPSG (Boro-Phospho-Silicate Glass) film 107 containing asignificantly high concentration of phosphorus (P) is formed directlybelow a planarization film 105 to fill recesses formed above photodiodes102.

The publication describes that the BPSG film with the high content ofphosphorus has a high density of recombination centers so thatelectron-hole pairs generated in a silicon oxide film can be effectivelyeliminated to reduce the number of holes trapped at a trapping centerand thereby to prevent the increase in interface state.

Japanese Unexamined Patent Publication No. 2001-250188 discloses anothermethod in which a transportation route is determined by calculation forminimizing the density of an energy beam among routes between places ofdispatch and arrival of a product so that transportation is made inaccordance with the given route. Many other methods have been proposed,i.e., one in which a packing material reducing the influence of anenergy beam to a minimum is used and another in which a housing of aproduct is made of a material protective against an energy beam.

In still another proposed method, after being transported, a CCD issubjected to a predetermined thermal treatment (for example, a thermaltreatment at 145° C. for about eight hours) before being incorporatedinto an apparatus to reduce an increased number of white defectes.

The above methods have the following problems.

In Japanese Unexamined Patent Publication No. Hei 8(1996)-18025, theBPSG film needs to contain a concentration of 5 mole % or more ofphosphorus (P₂O₅) or a concentration of 10 mol % or more of boron (B₂O₃)and phosphorus.

It is known that when a PSG (Phospho-Silicate Glass) film or a BPSG filmcontains a concentration of about 2 mol % or more of phosphorus in asemiconductor integrated circuit, a wiring metal (for example, Al)corrodes by the phosphorus with the lapse of use time.

To prevent this, in the CCD of Japanese Unexamined Patent PublicationNo. Hei 8(1996)-18025, the PBSG film containing the high concentrationof phosphorus is sandwiched between insulating films. However, there isa risk of the phosphorus being leaked when a crack is caused in theinsulating film. Also, an additional process is required fordepositing/processing the BPSG film.

In such a method as the one disclosed in Japanese Unexamined PatentPublication No. 2001-250188, transportation is made by way of a routeminimum in the density of an energy beam to lead the influence of theenergy beam to a minimum. The method is less than perfect since theintensity distribution of an energy beam varies every moment.

The method in which the material protective against a cosmic ray is usedfor the housing itself of the apparatus in which the CCD is incorporatedsuch as a video camera or the like is limited to a particular case dueto choice of materials or the like.

The method in which, after being transported, the CCD is subjected to apredetermined thermal treatment before being incorporated into theapparatus requires that equipments such as an oven and a tester,personnel with mastery of operations, and the like should be positionedat the assembly side, incurring extra costs. Also, if performed by theuser, the thermal treatment imposes a great deal of inconvenience on theuser. Further, it is difficult to install the expensive tester per userand thus to test the CCD after the thermal treatment, giving rise to aproblem in quality of the apparatus as a whole in which the CCD isincorporated.

The above influence of an energy beam is exerted not only on asolid-state image pickup device but also on all devices that utilizesemiconductors. For example, the above influence of an energy beam isexerted on semiconductor devices such as a memory, a logic, a bipolarand the like to cause device properties degradations such as aleak-current increase.

This means that difficulties are involved in packaging a device such asa CCD in a predetermined manner, incorporating the same into anapparatus such as a video camera or the like and then newly taking ameasure against particles with great energy such as a cosmic ray.

BRIEF SUMMARY

As a result of eager study, the present inventor has unexpectedly founda method capable of preventing the influence of an energy beam by asimple technique that does not require that a process of fabricating anelement be greatly changed, that special equipment be newly installed,or that transportation routes be individually determined bycalculations. Thus, the present invention has been achieved.

In accordance to the present invention, there is provided a method forfabricating a semiconductor device, comprising the steps of: forming anelement on a silicon substrate; packaging the element; and annealing thepackaged element before its transportation or long-term storage.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a schematic cross section illustrating a structure of a CCD;

FIG. 2 is a schematic cross section illustrating a structure of anotherCCD;

FIG. 3 is a flowchart for illustrating a method for fabricating asemiconductor device according to an example embodiment;

FIG. 4 is a flowchart for illustrating a conventional method forfabricating a semiconductor device;

FIG. 5 is a graph showing a change in the number of white defectes,before and after airfreight, in forty semiconductor devices packaged andthen annealed at 145° C. for 100 hours;

FIG. 6 is a graph showing a change in the number of white defectes,before and after airfreight, in fifty semiconductor devices packaged butnot annealed at 145° C.; and

FIG. 7 is a graph showing the white-defect failure rates, afterairfreight, of sets of semiconductor devices (each set made up of fifty)annealed at 145° C. under the condition that the annealing time ischanged for each set within the range of 0 and 200 hours.

DETAILED DESCRIPTION

One feature of the present invention is to subject a packaged element toa sufficient annealing treatment before its transportation (shipment) tothe user or before its long-term storage to reduce the number of defectssuch as white defects generated in a semiconductor device duringtransportation or packaging thereof.

Causes for a white defect are considered to be:

(1) An increase in trapping center density in a silicon oxide film or anincrease in interface state between silicon/the silicon oxide filmduring packaging of a semiconductor device due to contamination withimpurities such as heavy metal impurities which arise from a sealmaterial, an atmosphere or the like, water adsorption, and stressapplied in die bonding and

(2) Trapping of holes with less mobility among electrons/holes generatedin the silicon and in the silicon oxide film during exposure of thesemiconductor device to an energy beam such as a cosmic ray. Inaccordance with an example embodiment, the annealing treatment iscarried out to reduce the trapping center density in the silicon oxidefilm and the interface state at the silicon/the silicon oxide film andthereby to suppress the increase in leak current.

Consequently, it is possible to suppress the occurrence of defects suchas white defects resulting from a leak current caused by changes withtime after shipment and caused by an ionization damage from exposure toan energy beam.

The element according to the present invention is not particularlylimited. Examples of the element include solid-state image pickupdevices such as a CCD and a CMOS imager where prevention of whitedefects is expected, semiconductor devices such as a memory, a logic andbipolar where prevention of properties degradations such as a leakcurrent increase is expected, and modules in which these are contained.

The present invention is preferably applied, among the above elements,to solid-state image pickup devices such as a CCD and a CMOS imagerwhere a white defect resulting from energy exposure occurs andoutstanding degradations with time are observed. Examples of thesolid-state image pickup device include a CCD of the same structure asthe structures of the conventional CCDs shown in FIGS. 1 and 2.

A method for fabricating the element is not-particularly limited. Forexample, a known method may be used comprising the wafer steps offorming a plurality of element on a silicon wafer and sectioning thesilicon wafer into chips by dicing.

Then, the sectioned elements in the form of chips are each packaged. Inthe packaging step, which is not particularly limited, any knownmaterial and method may be used. Examples of the materials ofconstitution of a package include ceramics and plastics. Preferably, amaterial with a low radiant density of an alpha ray is used.

Further, the element is subjected to an annealing treatment. Theannealing treatment is preferably carried out under the temperature andtime at which the annealing treatment does not affect the element orpackage.

After the annealing treatment, the semiconductor device is tested,stored for an arbitrary term, and transported to the user, by whom thesemiconductor device is then incorporated into an apparatus. Inaccordance with the present invention, since the annealing treatment hassuppressed the occurrence of defects, an annealing treatment and atesting by the user can be omitted.

Hereafter, referring to a drawing, an explanation will be given to acase where the element is a CCD.

FIG. 3 shows a procedure followed by the present invention of fromproduction of a wafer for a CCD to incorporation of the CCD into anapparatus at the user side.

In a wafer step (1), a wafer having CCDs formed thereon is sectionedinto chips each having a CCD. Next, in a packaging step (2), each chipis mounted in a package made of ceramics or a plastic.

Though the packaging is performed with sufficient care paid to water andto contamination with impurities (such as heavy metal impurities), theinfluence thereof cannot completely be reduced to zero. Also, stressapplied to the chips in die bonding or the like during the packaging isdifficult to avoid. The water, contamination and stress may possiblycause changes with time after a semiconductor device is shipped to afactory by forming a trap level in a silicon oxide film and an interfacestate at the interface between a silicon substrate/the silicon oxidefilm.

Especially for a shipment to the user abroad, airfreight is required inmany cases because the time to deliver is short. Holes with lessmobility among electron-hole pairs generated in the silicon oxide filmdue to exposure to an energy beam during airfreight are trapped at atrapping center in the silicon oxide film or move in the film to reachthe interface between the silicon substrate and the silicon oxide film,creating a dangling bond in the silicon and thereby increasing interfacestate. The increase in interface state leads to the increase in leakcurrent and thus to the increase in the number of white defects.

In accordance with the present technology, it is preferable that, afterthe packaging, a sufficient annealing should be performed in anannealing step (3) at a temperature ranging from 100° C. to the heatresistant temperature of materials used in the solid-state image pickupdevice and in the package for about one hour to 200 hours. This makes itpossible not only to reduce a leak current arising from water andimpurities such as heavy metal but also to eliminate a trap level formedin the silicon oxide film and an interface state formed at the interfacebetween the silicon substrate/the silicon oxide film. Annealing at ahigher temperature for a longer time produces a higher effect. The upperlimit temperature can be properly set depending on the heat resistancesof a color filter, a lens, a package and a seal material of a CCD. Amore specific temperature range is 100 to 300° C.

In the case of a plastic package, a microlens of the CCD may possiblymelt or a package seal may possibly peel by the influence of watercontained in the package when the temperature is quickly raised to 140°C. or more. To prevent this, it is preferable that first, the package bedried at a temperature of about 70 to 100° C. and next, annealing isperformed at a temperature ranging from 140° C. to the heat resistanttemperature of the materials used in the CCD and in the package.

The packaging step and the annealing step are preferably performedsequentially.

Also, it is preferable that a testing step (4) should follow theannealing step (3). The testing step is not particularly limited, andany known testing step may be used.

The semiconductor device, in which the trap level and interface statehave been substantially eliminated by the annealing, is then transportedby airfreight (5) or the like to the user. Accordingly, the holes withless mobility among the electron-hole pairs generated in the siliconoxide film due to exposure of the semiconductor device to an energy beamcan be eliminated without being trapped to prevent white defects whichare otherwise generated after incorporation of the CCD into an apparatus(7) by the user (6).

Meanwhile, the shift of a coloring material for the color filter from apigment to a dye, the covering of a microlens with an inorganicmaterial, the improvement in an epoxy resin as a seal material, and theemployment of cement as the seal material have been made to realize aheat resistant temperature of about 200° C. and further to raise thepossibility of an annealing treatment at 300° C. Performing an annealingtreatment at a higher temperature for a longer period will be able toenhance the effect of the present invention.

Hereafter, the effect of the present invention will be explained indetail.

Forty semiconductor devices, one of which is shown in FIG. 1, werepackaged and annealed at 145° C. for 100 hours, followed by a trip fromJapan to Germany by airplane. FIG. 5 shows a change in the number ofwhite defects in the semiconductor devices after the trip.

It is understood from FIG. 5 that though the white defect level slightlyincreased in the annealed semiconductor devices, only one was foundfailed out of the forty semiconductor devices with a degradation rate of2.5%.

FIG. 6 shows a change in the number of white defects in fifty unannealedsemiconductor devices, one of which is shown in FIG. 1, after a tripfrom Japan to Germany.

It is understood from FIG. 6 that the white defect level significantlyincreased in four out of the fifty unannealed semiconductor devices witha degradation rate as high as 8%. This indicates that annealing canprevent white defectes resulting from exposure to a cosmic ray in asemiconductor device.

FIG. 7 shows the white-defect failure rate, after airfreight, of sets ofsemiconductor devices (each set made up of fifty) annealed at atemperature of 145° C. under the condition that the annealing time ischanged for each set within the range of 0 and 200 hours. In FIG. 7, aproduct at a zero annealing time corresponds to an unannealed product.The airfreight was made under the condition of a trip from Japan toGermany by airplane.

It is understood in FIG. 7 that even annealing at 145° C. for 10 hourscan prevent white defects and that annealing at 100 hours or more canprevent white defects more effectively.

FIG. 4 is a prior art procedure. An annealing step (6) is carried out bythe user (5) or by a local branch office or agent after airfreight (4).For example, annealing at 145° C. for about 8 hours has been generallyperformed because of constraints of facilities. This means that though alimited effect is produced in terms of elimination of a trap level andan interface state, no sufficient annealing has been performed. Inaccordance with the present invention, in which a large number ofsemiconductor devices can be annealed all at once in a semiconductorfactory, the constraints of facilities are reduced to make it possibleto perform sufficient annealing within the range of the heat resistanttemperatures of materials. Also, in prior arts in which after undergoingdevice processes, a semiconductor device is subjected to an annealingtreatment outside a semiconductor factory and incorporated into anapparatus without being retested, there is a risk that a semiconductordevice with a failure generated in the annealing treatment might beincorporated into the apparatus, while in the present invention, it ispossible to avoid the risk.

As has been described above, in accordance with the present invention,an element packaged in advance such as a CCD is subjected to sufficientannealing and then tested immediately before its shipment to the user.

For this reason, the present invention can reduce a surface leak currentcaused by contamination with impurities such as heavy metal which arisefrom a seal material, water absorption, and stress applied in diebonding or the like during packaging. Thereby, the present invention canprevent defects such as white defectes generated from the surface leakcurrent. Further, the present invention can reduce trapping centerdensity in the silicon oxide film and interface state at the siliconsubstrate/silicon oxide film to control the increase in dark currentcaused by trapping of holes with less mobility among electron/holesgenerated in the silicon oxide film due to exposure of the semiconductordevice to a beam with great energy.

Consequently, the present invention, in which the element packaged inadvance is subjected to sufficient annealing before being shipped to theuser, can suppress the occurrence of defects such as white defectesresulting from the leak current caused by changes with time and causedby ionization damage from exposure to an energy beam.

1. A method for fabricating a semiconductor device, comprising the stepsof: forming an element on a silicon substrate; packaging the resultingelement; driving the package element at 50° C. to 140° C. and thenannealing it at 100° C. to 300° C. before its transportation orlong-term storage; testing the annealed packaged element; transportingor long-term storing the tested packaged element; and incorporating thetransported or long-term stored packaged element into a device withoutannealing.
 2. The method for fabricating a semiconductor deviceaccording to claim 1, wherein the element is a CCD or a CMOS imager. 3.The method for fabricating a semiconductor device according to claim 1,wherein the annealing is performed at a temperature ranging from 100° C.to a heat resistant temperature of materials used in the element and ina package for 1–200 hours.
 4. The method for fabricating a semiconductordevice according to claim 3, wherein the annealing is performed at atemperature of 100–300° C.
 5. The method for fabricating a semiconductordevice according to claim 1, wherein a package is dried at a temperatureof 50–140° C. before the annealing.
 6. The method for fabricating asemiconductor device according to claim 5, wherein the drying isperformed for 20–120 minutes.
 7. The method for fabricating asemiconductor device according to claim 6, wherein the annealing isperformed at a temperature ranging from 100° C. to a heat resistanttemperature of materials used in the element and in a package for 1–200hours.
 8. The method for fabricating a semiconductor device according toclaim 7, wherein the annealing is performed at a temperature of 100–300°C.
 9. The method for fabricating a semiconductor device according toclaim 1, wherein the packaging step and the annealing step are performedsequentially.